On Thursday 19 May 2016 14:08:43 Andy Gross wrote:
> > + * - Tim
> > + */
> > +int qcom_tcsr_phy_sel(u32 val)
> > +{
> > + void __iomem *phy_select;
> > + int ret;
> > +
> > + phy_select = ioremap(USB2_PHY_SEL, 4);
> > +
> > + if (!phy_select) {
> > + ret = -ENOMEM;
> > + goto out;
> > + }
> > + /* Enable second PHY with the OTG port */
> > + writel(0x1, phy_select);
> > + ret = 0;
> > +out:
> > + iounmap(phy_select);
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(qcom_tcsr_phy_sel);
>
> I'd rather do something like what we did for the GSBI. It needed to
> change some phy related bits in the TCSR as well. We defined the TCSR
> as a syscon, with binding documentation under mfd. If we add a syscon
> entry and use it if it is present, we can deal with that pretty
> easily. The offsets change for each soc, and this would also fix that
> issue because we can change offset based on tcsr compat.
Works for me, but be aware that this will break the server chips,
as ACPI has no support for regmap devices.
I think that's fine, they should really handle this register access
in the firmware anyway rather than relying on a hardcoded MMIO
location.
Arnd
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