Add option to set initial output frequency of plls via "clock-frequency" property in pll's device tree node. This frequency will be set while pll driver probed. The usage example is setting CPU clock frequency on boot See discussion: https://www.mail-archive.com/linux-snps-arc at lists.infradead.org/msg02689.html Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> --- .../bindings/clock/snps,hsdk-pll-clock.txt | 5 ++++ .../devicetree/bindings/clock/snps,pll-clock.txt | 5 ++++ drivers/clk/axs10x/pll_clock.c | 34 ++++++++++++++++++++-- drivers/clk/clk-hsdk-pll.c | 34 ++++++++++++++++++++-- 4 files changed, 74 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt index c56c755..5703059 100644 --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt @@ -13,6 +13,10 @@ Required properties: - clocks: shall be the input parent clock phandle for the PLL. - #clock-cells: from common clock binding; Should always be set to 0. +Optional properties: +- clock-frequency: output frequency generated by pll in Hz which will be set +while probing. Should be a single cell. + Example: input_clk: input-clk { clock-frequency = <33333333>; @@ -25,4 +29,5 @@ Example: reg = <0x00 0x10>; #clock-cells = <0>; clocks = <&input_clk>; + clock-frequency = <1000000000>; }; diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt index 11fe487..5908f99 100644 --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register. - clocks: shall be the input parent clock phandle for the PLL. - #clock-cells: from common clock binding; Should always be set to 0. +Optional properties: +- clock-frequency: output frequency generated by pll in Hz which will be set +while probing. Should be a single cell. + Example: input-clk: input-clk { clock-frequency = <33333333>; @@ -25,4 +29,5 @@ Example: reg = <0x80 0x10>, <0x100 0x10>; #clock-cells = <0>; clocks = <&input-clk>; + clock-frequency = <100000000>; }; diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c index 25d8c24..3f4345d 100644 --- a/drivers/clk/axs10x/pll_clock.c +++ b/drivers/clk/axs10x/pll_clock.c @@ -11,6 +11,7 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/clk-provider.h> +#include <linux/clk.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/device.h> @@ -215,6 +216,25 @@ static const struct clk_ops axs10x_pll_ops = { .set_rate = axs10x_pll_set_rate, }; +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node) +{ + u32 requested_rate; + + /* If we specify initial pll output frequency try to set it */ + if (of_property_read_u32(node, "clock-frequency", &requested_rate)) + return; + + if (clk_prepare_enable(clk)) { + pr_err("Cannot enable %s clock.\n", node->name); + return; + } + + if (clk_set_rate(clk, requested_rate)) + pr_err("Cannot set %s clock rate.\n", node->name); + + pr_debug("Set %s clock to %u\n", node->name, requested_rate); +} + static int axs10x_pll_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -258,8 +278,15 @@ static int axs10x_pll_clk_probe(struct platform_device *pdev) return ret; } - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, - &pll_clk->hw); + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &pll_clk->hw); + if (ret) + return ret; + + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, dev->of_node); + + return 0; } static int axs10x_pll_clk_remove(struct platform_device *pdev) @@ -311,6 +338,9 @@ static void __init of_axs10x_pll_clk_setup(struct device_node *node) goto err_unregister_clk; } + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, node); + return; err_unregister_clk: diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c index bbf23717..74fd006 100644 --- a/drivers/clk/clk-hsdk-pll.c +++ b/drivers/clk/clk-hsdk-pll.c @@ -9,6 +9,7 @@ */ #include <linux/clk-provider.h> +#include <linux/clk.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/err.h> @@ -295,6 +296,25 @@ static const struct clk_ops hsdk_pll_ops = { .set_rate = hsdk_pll_set_rate, }; +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node) +{ + u32 requested_rate; + + /* If we specify initial pll output frequency try to set it */ + if (of_property_read_u32(node, "clock-frequency", &requested_rate)) + return; + + if (clk_prepare_enable(clk)) { + pr_err("Cannot enable %s clock.\n", node->name); + return; + } + + if (clk_set_rate(clk, requested_rate)) + pr_err("Cannot set %s clock rate.\n", node->name); + + pr_debug("Set %s clock to %u\n", node->name, requested_rate); +} + static int hsdk_pll_clk_probe(struct platform_device *pdev) { int ret; @@ -340,8 +360,15 @@ static int hsdk_pll_clk_probe(struct platform_device *pdev) return ret; } - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, - &pll_clk->hw); + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &pll_clk->hw); + if (ret) + return ret; + + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, dev->of_node); + + return 0; } static int hsdk_pll_clk_remove(struct platform_device *pdev) @@ -400,6 +427,9 @@ static void __init of_hsdk_pll_clk_setup(struct device_node *node) goto err_unmap_spec_regs; } + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, node); + return; err_unmap_spec_regs: -- 2.9.3
