Hi Thierry,
On Mon, 3 Mar 2025 at 16:10, Thierry Bultel
<thierry.bultel.yh@xxxxxxxxxxxxxx> wrote:
> > -----Original Message-----
> > From: Rob Herring <robh@xxxxxxxxxx>
> > Sent: lundi 3 mars 2025 14:36
> > To: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>
> > Cc: thierry.bultel@xxxxxxxxxxx; linux-renesas-soc@xxxxxxxxxxxxxxx;
> > geert@xxxxxxxxxxxxxx; Paul Barker <paul.barker.ct@xxxxxxxxxxxxxx>; Geert
> > Uytterhoeven <geert+renesas@xxxxxxxxx>; linux-kernel@xxxxxxxxxxxxxxx;
> > linux-serial@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx
> > Subject: Re: [PATCH v3 03/13] dt-bindings: serial: Add compatible for
> > Renesas RZ/T2H SoC in sci
> >
> > On Wed, Feb 26, 2025 at 02:09:22PM +0100, Thierry Bultel wrote:
> > > Document RZ/T2H (a.k.a r9a09g077) in SCI binding.
> > >
> > > Signed-off-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>
> > > Reviewed-by: Paul Barker <paul.barker.ct@xxxxxxxxxxxxxx>
> > > ---
> > > .../bindings/serial/renesas,sci.yaml | 64 ++++++++++++-------
> > > 1 file changed, 40 insertions(+), 24 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> > > b/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> > > index 64d3db6e54e5..2c4080283963 100644
> > > --- a/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> > > +++ b/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> > > @@ -9,9 +9,6 @@ title: Renesas Serial Communication Interface
> > > maintainers:
> > > - Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> > >
> > > -allOf:
> > > - - $ref: serial.yaml#
> > > -
> > > properties:
> > > compatible:
> > > oneOf:
> > > @@ -22,6 +19,8 @@ properties:
> > > - renesas,r9a07g054-sci # RZ/V2L
> > > - const: renesas,sci # generic SCI compatible UART
> > >
> > > + - const: renesas,r9a09g077-sci # RZ/T2H
> > > +
> >
> > Perhaps explain in the commit msg why the 'renesas,sci' is not applicable
> > for this chip.
>
> Would something like that be explicit enough ?
>
> "The SCI of RZ/T2H SoC (a.k.a r9a09g077), as a lot
> of similarities with other Renesas SoCs like G2L, G3S and V2L,
> but a different set of registers, that moreover are 32 bits instead
> of 16 bits.
> This is why the 'renesas,sci' fallback does not apply for it".
FTR, the registers being 32-bit instead of 8/16-bit wide is the least of
your problems... If it was just a SCI with 32-bit registers, you could
use "reg-io-width = <4>;" and "reg-shift = <2>;", and add support for
the latter to the driver (it already uses regshift on non-DT SuperH).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
