On 29/01/2025 16:37, Thierry Bultel wrote:
> RZ/T1 has SCIFA, 'T' is not relevant.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>
It'd be good to explain this better in the commit message, something like:
The comment was correct when it was added, at that time RZ/T1 was
the only SoC in the RZ/T line. Since then, further SoCs have been
added with RZ/T names which do not use the same SCIFA register
layout and so the comment is now misleading.
So we update the comment to explicitly reference only RZ/T1 SoCs.
> ---
> drivers/tty/serial/sh-sci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index 924b803af440..5ba25a6a5432 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -291,7 +291,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
> },
>
> /*
> - * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
> + * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1
Please keep the full stop at the end of the sentence for consistency.
> * It looks like a normal SCIF with FIFO data, but with a
> * compressed address space. Also, the break out of interrupts
> * are different: ERI/BRI, RXI, TXI, TEI, DRI.
Thanks,
--
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