On Thu, Jan 9, 2025, at 13:08, WangYuli wrote:
> [ General description per its product manual: ]
> The IT8768E-I is a highly integrated Super I/O using the Low Pin
> Count Interface. The device’s LPC interface complies with Intel
> "LPC Interface Specification Rev. 1.1”. The IT8768E-I is ACPI &
> LANDesk compliant.
>
> Integrated in the IT8768E-I are five logical devices, which can
> be individually enabled or disabled via software configuration
> registers, and four 16C550standard compatible enhanced UARTs
> perofrmacing asynchronous communication. The devices also provide
> GPIO port controlling up to 12 GPIO pins.
>
> The IT8768E-I utilizes power-saving circuitry to reduce power
> consumption, and once a logical device is disabled, the inputs
> are inhibited with the clock disabled and the outputs are
> tri-stated. The device requires a single 24/48 MHz clock input
> and operates with +3.3V power supply. The IT8768E-I is available
> in 48-pin LQFP.
>
> It has been determined that this chip is currently employed within
> YIHUA STS-320 intelligent teller terminals utilizing
> PCBA F21-2401 D2000 MB VerA LF motherboards.
Can you explain why this isn't done as part of
drivers/tty/serial/8250/8250_pnp.c?
I see nothing unusual in here that requires a custom driver.
Arnd
