On Mon, 4 Nov 2024, Jiri Slaby wrote:
> > > THRE only signals there is a space for one character.
> >
> > Nope[1]:
> >
> > "In the FIFO mode, THRE is set when the transmit FIFO is empty; it is
> > cleared when at least one byte is written to the transmit FIFO."
>
> Hmm, I was confused by NXP's 16c650b [1] datasheet then (or I cannot parse):
> ===
> The THR empty flag in the LSR register will be set to a logic 1 when the
> transmitter is empty or when data is transferred to the TSR. Note that a write
> operation can be performed when the THR empty flag is set
> (logic 0 = FIFO full; logic 1 = at least one FIFO location available).
> ===
This description seems broken indeed and I find your interpretation of it
correct. I do hope this is just an editorial mistake with the NXP device.
> But indeed in the LSR[5] bit description, they state:
> ===
> In the FIFO mode, this bit is set when the transmit FIFO is
> empty; it is cleared when at least 1 byte is written to the transmit FIFO.
> ===
FWIW I chased documentation for the original 16550A device and it uses
analogous wording[1]:
"Bit 5: This bit is the Transmitter Holding Register Empty (THRE)
indicator. Bit 5 indicates that the UART is ready to
accept a new character for transmission. In addition, this bit
causes the UART to issue an interrupt to the CPU when the
Transmit Holding Register Empty Interrupt enable is set
high. The THRE bit is set to a logic 1 when a character is
transferred from the Transmitter Holding Register into the
Transmitter Shift Register. The bit is reset to logic 0 concur-
rently with the loading of the Transmitter Holding Register
by the CPU. In the FIFO mode this bit is set when the XMIT
FIFO is empty; it is cleared when at least 1 byte is written to
the XMIT FIFO."
It further documents polled operation for THRE[2]:
"LSR5 will indicate when the XMIT FIFO is empty."
and provides further details as to the transmit FIFO[3]:
"The NS16550A transmitter optimizes the CPU/UART data
transaction via the following features:
"1. The depth of the Transmitter (Tx) FIFO ensures that as
many as 16 characters can be transferred when the
CPU services the Tx interrupt. Once again, this effec-
tively buffers the CPU transfer rate from the serial data
rate.
"2. The Transmitter (Tx) FIFO is similar in structure to
FIFOs the user may have previously set up in RAM. The
Tx depth allows the CPU to load 16 characters each
time it switches context to the service routine. This re-
duces the impact of the CPU time lost in context switch-
ing.
"3. Since a time lag in servicing an asynchronous transmit-
ter usually has no penalty, CPU latency time is of no
concern to transmitter operation."
This design choice may result in "choppy" transmission due to the transmit
handler invocation latency, but as noted above it is intentional. DMA can
be used with the NS16550A if it is required to avoid this issue, and later
compatible UART designs such as the 650 give more flexibility as to the Tx
FIFO fill level trigger threshold.
References:
[1] National Semiconductor Corporation, "Microcommunication Elements
Databook, 1987 Edition", "NS16550A Universal Asynchronous
Receiver/Transmitter with FIFOs", Section 8.4 "LINE STATUS REGISTER",
p. 2-73
[2] same, Section 8.12 "FIFO POLLED MODE OPERATION", p. 2-75
[3] same, Martin S. Michael, Daniel G. Durich, Application Note 491, "The
NS 16550A: UART Design and Application Considerations", Section 1.0
"Design Considerations and Operation of the New UART Features", p. 5-4
Available from:
<http://bitsavers.org/components/national/_dataBooks/1987_National_Microcommunications_Elements_Data_Book.pdf>.
HTH,
Maciej
