On Fri, Sep 6, 2024 at 6:54 PM Florian Fainelli
<florian.fainelli@xxxxxxxxxxxx> wrote:
>
> The write to RP2_GLOBAL_CMD followed by an immediate read of
> RP2_GLOBAL_CMD in rp2_reset_asic() is intented to flush out the write,
> however by then the device is already in reset and cannot respond to a
> memory cycle access.
>
> On platforms such as the Raspberry Pi 4 and others using the
> pcie-brcmstb.c driver, any memory access to a device that cannot respond
> is met with a fatal system error, rather than being substituted with all
> 1s as is usually the case on PC platforms.
>
> Swapping the delay and the read ensures that the device has finished
> resetting before we attempt to read from it.
>
> Fixes: 7d9f49afa451 ("serial: rp2: New driver for Comtrol RocketPort 2 cards")
> Suggested-by: Jim Quinlan <james.quinlan@xxxxxxxxxxxx>
> Signed-off-by: Florian Fainelli <florian.fainelli@xxxxxxxxxxxx>
> ---
> drivers/tty/serial/rp2.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/tty/serial/rp2.c b/drivers/tty/serial/rp2.c
> index 4132fcff7d4e..8bab2aedc499 100644
> --- a/drivers/tty/serial/rp2.c
> +++ b/drivers/tty/serial/rp2.c
> @@ -577,8 +577,8 @@ static void rp2_reset_asic(struct rp2_card *card, unsigned int asic_id)
> u32 clk_cfg;
>
> writew(1, base + RP2_GLOBAL_CMD);
> - readw(base + RP2_GLOBAL_CMD);
> msleep(100);
> + readw(base + RP2_GLOBAL_CMD);
Since the assumed purpose of the readw() was to flush the writew(),
would it make sense to add a barrier after the writew()?
Regards,
Jim Quinlan
Broadcom STB/CM
> writel(0, base + RP2_CLK_PRESCALER);
>
> /* TDM clock configuration */
> --
> 2.43.0
>
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