On 22. 04. 24, 14:00, Konstantin P. wrote:
On Mon, Apr 22, 2024 at 9:30 AM Jiri Slaby <jirislaby@xxxxxxxxxx> wrote:
On 20. 04. 24, 20:22, Konstantin Pugin wrote:
From: Konstantin Pugin <ria.freelander@xxxxxxxxx>
XR20M1172 register set is mostly compatible with SC16IS762, but it has
a support for additional division rates of UART with special DLD register.
So, add handling this register by appropriate devicetree bindings.
...
--- a/drivers/tty/serial/sc16is7xx.c
+++ b/drivers/tty/serial/sc16is7xx.c
...
@@ -555,18 +578,43 @@ static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg)
return reg == SC16IS7XX_RHR_REG;
}
+static bool sc16is7xx_has_dld(struct device *dev)
+{
+ struct sc16is7xx_port *s = dev_get_drvdata(dev);
+
+ if (s->devtype == &xr20m1172_devtype)
+ return true;
+ return false;
:) so this should simply be:
return s->devtype == &xr20m1172_devtype;
I especially want to avoid this construction, because it will lead to
idea than we does not have other
DLD-capable UARTS, which is simply not true, there is, for example,
XR20M1280 UART, which has roughly the same register set
(https://www.alldatasheet.com/datasheet-pdf/pdf/445109/EXAR/XR20M1280.html).
I simply do not have other devices, so I do not
want to risk sending untested patches upstream.
Sorry, what?
--
js
suse labs
