On Mon, Apr 22, 2024 at 03:37:55PM +0300, Konstantin Pugin wrote:
> From: Konstantin Pugin <ria.freelander@xxxxxxxxx>
>
> The hardware supports both RTS_ON_SEND and RTS_AFTER_SEND modes, but
> after the commit 4afeced55baa ("serial: core: fix sanitizing check for
> RTS settings") we always end up with SER_RS485_RTS_AFTER_SEND set and
> always write to the register field SC16IS7XX_EFCR_RTS_INVERT_BIT, which
> breaks some hardware using these chips.
LGTM, but I leave it to Hugo for testing and other comments, if any,
as I don't have a HW.
Reviewed-by: Andy Shevchenko <andy@xxxxxxxxxx>
--
With Best Regards,
Andy Shevchenko
