On 18. 04. 24, 19:06, Konstantin Pugin wrote:
From: Konstantin Pugin <ria.freelander@xxxxxxxxx>
XR20M1172 register set is mostly compatible with SC16IS762, but it has
a support for additional division rates of UART with special DLD register.
So, add handling this register by appropriate devicetree bindings.
Reviewed-by: Vladimir Zapolskiy <vz@xxxxxxxxx>
Signed-off-by: Konstantin Pugin <ria.freelander@xxxxxxxxx>
---
drivers/tty/serial/sc16is7xx.c | 55 +++++++++++++++++++++++++++++++---
1 file changed, 51 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c
index a300eebf1401..59376c637467 100644
--- a/drivers/tty/serial/sc16is7xx.c
+++ b/drivers/tty/serial/sc16is7xx.c
...
@@ -556,16 +579,33 @@ static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg)
static int sc16is7xx_set_baud(struct uart_port *port, int baud)
{
+ struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
- u8 lcr;
+ unsigned long clk = port->uartclk, div, div16;
+ bool has_dld = s->devtype->has_dld;
+ u8 dld_mode = XR20M117X_DLD_16X;
u8 prescaler = 0;
- unsigned long clk = port->uartclk, div = clk / 16 / baud;
+ u8 divisor = 16;
+ u8 lcr;
+
+ if (has_dld && DIV_ROUND_CLOSEST(clk, baud) < 16)
+ divisor = 1 << (fls(DIV_ROUND_CLOSEST(clk, baud)) - 1);
Do you mimic roundup_pow_of_two()?
--
js
suse labs
