On Tue, Jan 30, 2024 at 10:52:41AM +0000, Rengarajan.S@xxxxxxxxxxxxx wrote: > On Sun, 2024-01-28 at 17:27 +0200, Andy Shevchenko wrote: > > On Thu, Jan 25, 2024 at 03:36:19PM +0530, Rengarajan S wrote: ... > > > + /* > > > + * Microchip PCI1XXXX UART supports maximum baud rate up to 4 > > > Mbps > > > + */ > > > + if (up->port.type == PORT_MCHP16550A) > > > + max = 4000000; > > > > No. Please refactor the way the 8250_port won't be modified. > > > > Also you have a define for this constant, use it. > > The current UART clk in MCHP Ports in pci1xxxx.c is set to 62.5 MHz in > order to support fractional baud rates which enables generation of > acceptable baud rate and lower error percentage from any available > frequency. With 62.5 MHz the maximum supported baud rate supported as > per serial_8250_get_baud_rate is 3.9 Mbps. In order to extend the > support to 4 Mbps we had hardcoded the max value to 4 Mbps. Since, baud > rate is calculated here we needed to make these changes in 8250_port > and could not find a way to handle as part 8250_pci1xxxx. Can you let > us know any alternatives to address this upper(max) limit? Update port->uartclk accordingly in your driver, see how other 8250_* drivers do that (e.g., 8250_mid). So, it will no go with hack in the 8250_port. -- With Best Regards, Andy Shevchenko
