Hi Rob,
On 12/21/23 22:53, Rob Herring wrote:
On Tue, Dec 12, 2023 at 04:23:46PM +0100, Gatien Chevallier wrote:
Document RIFSC (RIF security controller). RIFSC is a firewall controller
composed of different kinds of hardware resources.
Signed-off-by: Gatien Chevallier <gatien.chevallier@xxxxxxxxxxx>
---
Changes in V6:
- Renamed access-controller to access-controllers
- Removal of access-control-provider property
- Removal of access-controller and access-controller-names
declaration in the patternProperties field. Add
additionalProperties: true in this field.
Changes in V5:
- Renamed feature-domain* to access-control*
Changes in V2:
- Corrected errors highlighted by Rob's robot
- No longer define the maxItems for the "feature-domains"
property
- Fix example (node name, status)
- Declare "feature-domain-names" as an optional
property for child nodes
- Fix description of "feature-domains" property
.../bindings/bus/st,stm32mp25-rifsc.yaml | 96 +++++++++++++++++++
1 file changed, 96 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
new file mode 100644
index 000000000000..95aa7f04c739
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 Resource isolation framework security controller
+
+maintainers:
+ - Gatien Chevallier <gatien.chevallier@xxxxxxxxxxx>
+
+description: |
+ Resource isolation framework (RIF) is a comprehensive set of hardware blocks
+ designed to enforce and manage isolation of STM32 hardware resources like
+ memory and peripherals.
+
+ The RIFSC (RIF security controller) is composed of three sets of registers,
+ each managing a specific set of hardware resources:
+ - RISC registers associated with RISUP logic (resource isolation device unit
+ for peripherals), assign all non-RIF aware peripherals to zero, one or
+ any security domains (secure, privilege, compartment).
+ - RIMC registers: associated with RIMU logic (resource isolation master
+ unit), assign all non RIF-aware bus master to one security domain by
+ setting secure, privileged and compartment information on the system bus.
+ Alternatively, the RISUP logic controlling the device port access to a
+ peripheral can assign target bus attributes to this peripheral master port
+ (supported attribute: CID).
+ - RISC registers associated with RISAL logic (resource isolation device unit
+ for address space - Lite version), assign address space subregions to one
+ security domains (secure, privilege, compartment).
+
+properties:
+ compatible:
+ contains:
+ const: st,stm32mp25-rifsc
This needs to be exact and include 'simple-bus'. You'll need a custom
'select' with the above to avoid matching all other 'simple-bus' cases.
With that,
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
Thank you for the review,
I'll update this for the next version whilst applying your tag
Gatien
