On Tue, 17 Oct 2023 at 09:52, Chanwoo Choi <chanwoo@xxxxxxxxxx> wrote: > > On 23. 10. 12. 03:48, Peter Griffin wrote: > > These plls are found in the Tensor gs101 SoC found in the Pixel 6. > > > > pll0516x: Integer PLL with high frequency > > pll0517x: Integer PLL with middle frequency > > pll0518x: Integer PLL with low frequency > > > > PLL0516x > > FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV) > > > > PLL0517x and PLL0518x > > FOUT = (MDIV * FIN)/PDIV*2^SDIV) > > > > The PLLs are similar enough to pll_0822x that the same code can handle > > both. The main difference is the change in the fout formula for the > > high frequency 0516 pll. > > > > Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor. > > MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x. > > > > When defining the PLL the "con" parameter should be set to CON3 > > register, like this > > > > PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", > > PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, > > NULL), > > > > Signed-off-by: Peter Griffin <peter.griffin@xxxxxxxxxx> > > --- > > drivers/clk/samsung/clk-pll.c | 9 ++++++++- > > drivers/clk/samsung/clk-pll.h | 3 +++ > > 2 files changed, 11 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c > > index 74934c6182ce..4ef9fea2a425 100644 > > --- a/drivers/clk/samsung/clk-pll.c > > +++ b/drivers/clk/samsung/clk-pll.c > > @@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, > > pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK; > > sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; > > > > - fvco *= mdiv; > > + if (pll->type == pll_0516x) > > + fvco = fvco * 2 * mdiv; > > + else > > + fvco *= mdiv; > > + > > do_div(fvco, (pdiv << sdiv)); > > > > return (unsigned long)fvco; > > @@ -1316,6 +1320,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, > > case pll_1417x: > > case pll_0818x: > > case pll_0822x: > > + case pll_0516x: > > + case pll_0517x: > > + case pll_0518x: > > pll->enable_offs = PLL0822X_ENABLE_SHIFT; > > pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; > > if (!pll->rate_table) > > diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h > > index 0725d485c6ee..ffd3d52c0dec 100644 > > --- a/drivers/clk/samsung/clk-pll.h > > +++ b/drivers/clk/samsung/clk-pll.h > > @@ -38,6 +38,9 @@ enum samsung_pll_type { > > pll_0822x, > > pll_0831x, > > pll_142xx, > > + pll_0516x, > > + pll_0517x, > > + pll_0518x, > > }; > > > > #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ > > I replied it with ack before. Again, reply it with ack. > > Acked-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx> Thanks Chanwoo. I will add that in v4