Add optional gpio property to uartps node and reference to rs485.yaml On Xilinx/AMD Kria SOM KD240 board rs485 connects via TI ISOW1432 Transceiver device, where one GPIO is used for driving DE/RE signals. With rs485 half duplex configuration, DE and RE shorts to each other, and at a time, any node acts as either a driver or a receiver. Here, DE - Driver enable. If pin is floating, driver is disabled. RE - Receiver enable. If pin is floating, receiver buffer is disabled. For more deatils, please find below link which contains Transceiver device(ISOW1432) datasheet https://www.ti.com/lit/ds/symlink/isow1432.pdf?ts=1682607122706&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FISOW1432%252Fpart-details%252FISOW1432DFMR%253FkeyMatch%253DISOW1432DFMR%2526tisearch%253Dsearch-everything%2526usecase%253DOPN xlnx,phy-ctrl-gpios is optional property, because it is not required for uart console node. Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@xxxxxxx> --- Changes for V2: Modify optional gpio name to xlnx,phy-ctrl-gpios. Update commit description. --- Documentation/devicetree/bindings/serial/cdns,uart.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml index a8b323d7bf94..cf8ef55ba210 100644 --- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml @@ -46,6 +46,11 @@ properties: power-domains: maxItems: 1 + xlnx,phy-ctrl-gpios: + description: Optional GPIO to control transmit/receive on RS485 phy + in halfduplex mode. + maxItems: 1 + required: - compatible - reg @@ -55,6 +60,7 @@ required: allOf: - $ref: serial.yaml# + - $ref: rs485.yaml# - if: properties: compatible: -- 2.25.1
