From: Hugo Villeneuve <hvilleneuve@xxxxxxxxxxxx> Replace 740/750/760 with generic terms like 74x/75x/76x to account for variants like 741, 752 and 762. Signed-off-by: Hugo Villeneuve <hvilleneuve@xxxxxxxxxxxx> Reviewed-by: Lech Perczak <lech.perczak@xxxxxxxxxxxxxxx> --- drivers/tty/serial/sc16is7xx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index f61d98e09dc3..f89eba15ddcd 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -223,7 +223,7 @@ * trigger levels. Trigger levels from 4 characters to 60 characters are * available with a granularity of four. * - * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the + * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the * trigger level setting defined in FCR. If TLR has non-zero trigger level value * the trigger level defined in FCR is discarded. This applies to both transmit * FIFO and receive FIFO trigger level setting. @@ -234,7 +234,7 @@ #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) -/* IOControl register bits (Only 750/760) */ +/* IOControl register bits (Only 75x/76x) */ #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ #define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */ #define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */ @@ -249,9 +249,9 @@ #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode * 0 = rate upto 115.2 kbit/s - * - Only 750/760 + * - Only 75x/76x * 1 = rate upto 1.152 Mbit/s - * - Only 760 + * - Only 76x */ /* EFR register bits */ base-commit: 3f86ed6ec0b390c033eae7f9c487a3fea268e027 -- 2.30.2
