On 2023. 06. 07. 14:39, Sherry Sun wrote:
> Hi Robert,
>
> No, please don’t do that.
> I agree with you that the LPUART RM has a false statement, the Receive Watermark actually can be greater than or equal to 0, but this doesn’t mean that it must be 0.
> And the false statement has nothing to do with the code here. The code here aims to set the different values for lpuart interrupt case and dma case, and force the rx watermark for dma case to 0, which is unreasonable.
> We have already set the watermark in lpuart32_setup_watermark(), it works for both interrupt and dma case, you can set the rx_watermark value for different platforms according to your requirements, from 0 ~ FIFO[RXFIFOSIZE]-1.
>
> Best Regards
> Sherry
>
I'm working on an LS1028A-based (actually LS1027A) unit. Having the watermark set to 1 is basically making the LPUART unusable. DMA is enabled on this platform. The last character always gets stuck in the receive buffer, and I receive only the previous one. So the WATER register's content after sending one character to the unit (but not receiving it in Linux on the unit) is the following:
0x0226001c: 01010000
Which means, watermark is set to 1, there's one character waiting in the FIFO, and there was no DMA transaction to move out that character from the FIFO into the DMA RX buffer.
The RM says: "When the number of datawords in the receive FIFO/buffer is greater than the value in this register field, an interrupt or a DMA request is generated." So if I get it right, having the watermark set to 1, will never generate a DMA request when only a single character is sent. The RX timeout function with DMA will help nothing here, as there will be nothing in the RX buffer.
But if DMA is NOT used (interrupt based receive), we can set whatever we want to watermark, as the timeout function will collect the received bytes from the FIFO.
Best regards,
Robert
