On 04/05/2023 05:37, Jacky Huang wrote: > From: Jacky Huang <ychuang3@xxxxxxxxxxx> > > The clock controller generates clocks for the whole chip, including > system clocks and all peripheral clocks. This driver support ma35d1 > clock gating, divider, and individual PLL configuration. > > There are 6 PLLs in ma35d1 SoC: > - CA-PLL for the two Cortex-A35 CPU clock > - SYS-PLL for system bus, which comes from the companion MCU > and cannot be programmed by clock controller. > - DDR-PLL for DDR > - EPLL for GMAC and GFX, Display, and VDEC IPs. > - VPLL for video output pixel clock > - APLL for SDHC, I2S audio, and other IPs. > CA-PLL has only one operation mode. > DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3 > operation modes: integer mode, fraction mode, and spread specturm mode. > > Signed-off-by: Jacky Huang <ychuang3@xxxxxxxxxxx> > --- > drivers/clk/Makefile | 1 + > drivers/clk/nuvoton/Kconfig | 19 + > drivers/clk/nuvoton/Makefile | 4 + > drivers/clk/nuvoton/clk-ma35d1-divider.c | 140 ++++ > drivers/clk/nuvoton/clk-ma35d1-pll.c | 365 +++++++++ > drivers/clk/nuvoton/clk-ma35d1.c | 948 +++++++++++++++++++++++ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
