> -----Original Message-----
> From: Ilpo Järvinen <ilpo.jarvinen@xxxxxxxxxxxxxxx>
> Sent: Friday, April 21, 2023 1:54 PM
> To: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>; Biju Das
> <biju.das.jz@xxxxxxxxxxxxxx>
> Cc: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>; Jiri Slaby
> <jirislaby@xxxxxxxxxx>; Yoshinori Sato <ysato@xxxxxxxxxxxxxxxxxxxx>; linux-
> serial <linux-serial@xxxxxxxxxxxxxxx>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>; linux-renesas-soc@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH v4 5/5] tty: serial: sh-sci: Fix end of transmission on
> SCI
>
> On Fri, 21 Apr 2023, Geert Uytterhoeven wrote:
>
> > Hi Biju,
> >
> > On Wed, Apr 12, 2023 at 4:51 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> > > We need to set TE to "0" (i.e., disable serial transmission) to get
> > > the expected behavior of the end of serial transmission.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/tty/serial/sh-sci.c
> > > +++ b/drivers/tty/serial/sh-sci.c
> > > @@ -847,6 +847,11 @@ static void sci_transmit_chars(struct uart_port
> *port)
> > > } else if (!uart_circ_empty(xmit) && !stopped) {
> > > c = xmit->buf[xmit->tail];
> > > xmit->tail = (xmit->tail + 1) &
> > > (UART_XMIT_SIZE - 1);
> > > + } else if (port->type == PORT_SCI &&
> uart_circ_empty(xmit)) {
> > > + ctrl = serial_port_in(port, SCSCR);
> > > + ctrl &= ~SCSCR_TE;
> > > + serial_port_out(port, SCSCR, ctrl);
> > > + return;
> >
> > So nothing after the while loop should be done anymore?
> > What about clearing SCSCR_TE in sci_stop_tx() (which is called after
> > the while loop) instead?
>
> Yes, this added fragment doesn't really seem to belong into the tx loop.
The difference is, Maybe this IP doesn't have FIFO compared to other SCIF IPs.
and Carriage return is not handled properly without this fix.
> The right direction would be to aim towards converting the whole tx loop
> into using uart_port_tx_limited().
But looks like this change will have bigger impact as we need to test wide range of SoCs
in both interrupt and DMA mode.
Cheers,
Biju
