On 18/03/2023 07:07, Jacky Huang wrote:
>
>>
>>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) |
>>> + IRQ_TYPE_LEVEL_HIGH)>;
>>> + };
>>> +
>>> + uart0:serial@40700000 {
>>> + compatible = "nuvoton,ma35d1-uart";
>>> + reg = <0x0 0x40700000 0x0 0x100>;
>>> + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk UART0_GATE>;
>>> + status = "okay";
>> Why? Drop the line... or convert it to disabled. Otherwise, why every
>> SoC has serial0 enabled? Is it used internally?
>
>
> uart0 is on all the way since this SoC booting from the MaskROM boot code,
>
> load arm-trusted-firmware, load bootloader, and finally load linux kernel.
>
> uart0 is also the Linux console.
Are you sure? Maybe my board has UART0 disconnected.
Best regards,
Krzysztof
