On Thu, 8 Dec 2022, Kumaravel Thiagarajan wrote:
> pci1xxxx uart supports RS485 mode of operation in the hardware with
> auto-direction control with configurable delay for releasing RTS after
> the transmission. This patch adds support for the RS485 mode.
>
> Co-developed-by: Tharun Kumar P <tharunkumar.pasumarthi@xxxxxxxxxxxxx>
> Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@xxxxxxxxxxxxx>
> Signed-off-by: Kumaravel Thiagarajan <kumaravel.thiagarajan@xxxxxxxxxxxxx>
> ---
> Changes in v7:
> - No Change
>
> Changes in v6:
> - Modified datatype of delay_in_baud_periods to u64 to avoid overflows
>
> Changes in v5:
> - Removed unnecessary assignments
> - Corrected styling issues in comments
>
> Changes in v4:
> - No Change
>
> Changes in v3:
> - Remove flags sanitization in driver which is taken care in core
>
> Changes in v2:
> - move pci1xxxx_rs485_config to a separate patch with
> pci1xxxx_rs485_supported.
> ---
> drivers/tty/serial/8250/8250_pci1xxxx.c | 49 +++++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c
> index be554e2d884b..9f0da264314a 100644
> --- a/drivers/tty/serial/8250/8250_pci1xxxx.c
> +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c
> @@ -145,6 +145,53 @@ static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud,
> port->membase + UART_BAUD_CLK_DIVISOR_REG);
> }
>
> +static int pci1xxxx_rs485_config(struct uart_port *port,
> + struct ktermios *termios,
> + struct serial_rs485 *rs485)
> +{
> + u32 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG);
> + u64 delay_in_baud_periods;
> + u32 baud_period_in_ns;
> + u32 data = 0;
> +
> + /*
> + * pci1xxxx's uart hardware supports only RTS delay after
> + * Tx and in units of bit times to a maximum of 15
> + */
> + if (rs485->flags & SER_RS485_ENABLED) {
> + data = ADCL_CFG_EN | ADCL_CFG_PIN_SEL;
> +
> + if (!(rs485->flags & SER_RS485_RTS_ON_SEND))
> + data |= ADCL_CFG_POL_SEL;
> +
> + if (rs485->delay_rts_after_send) {
> + baud_period_in_ns =
> + FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) *
> + UART_BIT_SAMPLE_CNT;
> + delay_in_baud_periods =
> + rs485->delay_rts_after_send * NSEC_PER_MSEC /
> + baud_period_in_ns;
> + delay_in_baud_periods =
> + min_t(u64, delay_in_baud_periods,
> + FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK));
> + data |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK,
> + delay_in_baud_periods);
> + rs485->delay_rts_after_send =
> + baud_period_in_ns * delay_in_baud_periods /
> + NSEC_PER_MSEC;
div_u64() or cast+comment if you can prove you never need the high-word at
this point.
But why you even need u64 because delay_rts_after_send is limited to
RS485_MAX_RTS_DELAY (=100) by serial core? 100 * NSEC_PER_MSEC doesn't
overflow u32.
--
i.
