Re: [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V

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On 05. 12. 22, 6:00, Bin Meng wrote:
...
--- a/drivers/tty/serial/earlycon-arm-semihost.c
+++ b/drivers/tty/serial/earlycon-arm-semihost.c
...
@@ -23,7 +27,18 @@
   */
  static void smh_putc(struct uart_port *port, unsigned char c)
  {
-#ifdef CONFIG_ARM64
+#if defined(CONFIG_RISCV)
+	asm volatile("addi    a1, %0, 0\n"
+		     "addi    a0, zero, 3\n"
+		     ".balign 16\n"
+		     ".option push\n"
+		     ".option norvc\n"
+		     "slli    zero, zero, 0x1f\n"
+		     "ebreak\n"
+		     "srai    zero, zero, 0x7\n"
+		     ".option pop\n"
+		     : : "r" (&c) : "a0", "a1", "memory");
+#elif defined(CONFIG_ARM64)
  	asm volatile("mov  x1, %0\n"
  		     "mov  x0, #3\n"
  		     "hlt  0xf000\n"

Hmm, can we implement all those smh_putc() variants in respective arch/*/include/semihost.h instead?

thanks,
--
js
suse labs




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