On Mon, Oct 31, 2022 at 11:24 AM <Tharunkumar.Pasumarthi@xxxxxxxxxxxxx> wrote:
> > -----Original Message-----
> > From: Andy Shevchenko <andy.shevchenko@xxxxxxxxx>
> > Sent: Monday, October 3, 2022 2:53 PM
...
> > > + [PORT_MCHP16550A] = {
> > > + .name = "MCHP16550A",
> > > + .fifo_size = 256,
> > > + .tx_loadsz = 256,
> > > + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
> > > + .rxtrig_bytes = {2, 66, 130, 194},
> > > + .flags = UART_CAP_FIFO,
> > > + },
> >
> > Can you assign this in ->setup() or so instead of adding a new port type?
>
> If I understand correctly, you suggest doing something like this inside pci1xxxx_setup() API:
>
> pci1xxxx_setup(.., uart_8250_port *port, ..) {
> ..
> port->port.fifosize = 256;
> port->tx_loadsz = 256;
> port->capabilities = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01;
> ..
> }
>
> instead of adding new port type PORT_MCHP16550A.
Yes, something like this.
> But, if I do this, I cannot use sysfs interface for updating rx_trig_bytes right?
Maybe, I don't remember by heart that part of the code. But why do you
need that ABI in the first place?
--
With Best Regards,
Andy Shevchenko
