When the PWM driver was changed to disable clocks if no PWMs are enabled,
it ended up also disabling the shared parent with the UART, since the
UART doesn't do any clock enablement on its own.
To avoid these surprises, add clk_prepare_enable/clk_disable_unprepare
calls.
Fixes: ace41d7564e655 ("pwm: sifive: Ensure the clk is enabled exactly once per running PWM")
Cc: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx>
Cc: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
Cc: Palmer Dabbelt <palmer@xxxxxxxxxxx>
Cc: Paul Walmsley <paul.walmsley@xxxxxxxxxx>
Signed-off-by: Olof Johansson <olof@xxxxxxxxx>
---
drivers/tty/serial/sifive.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/sifive.c b/drivers/tty/serial/sifive.c
index 5c3a07546a58..751f98068806 100644
--- a/drivers/tty/serial/sifive.c
+++ b/drivers/tty/serial/sifive.c
@@ -950,23 +950,28 @@ static int sifive_serial_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "unable to find controller clock\n");
return PTR_ERR(clk);
}
+ clk_prepare_enable(clk);
id = of_alias_get_id(pdev->dev.of_node, "serial");
if (id < 0) {
dev_err(&pdev->dev, "missing aliases entry\n");
- return id;
+ r = id;
+ goto probe_out1;
}
#ifdef CONFIG_SERIAL_SIFIVE_CONSOLE
if (id > SIFIVE_SERIAL_MAX_PORTS) {
dev_err(&pdev->dev, "too many UARTs (%d)\n", id);
- return -EINVAL;
+ r = -EINVAL;
+ goto probe_out1;
}
#endif
ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL);
- if (!ssp)
- return -ENOMEM;
+ if (!ssp) {
+ r = -ENOMEM;
+ goto probe_out1;
+ }
ssp->port.dev = &pdev->dev;
ssp->port.type = PORT_SIFIVE_V0;
@@ -1028,6 +1033,7 @@ static int sifive_serial_probe(struct platform_device *pdev)
probe_out2:
clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
probe_out1:
+ clk_disable_unprepare(clk);
return r;
}
--
2.30.2
