On Thu, Jul 14, 2022 at 03:26:30PM +0000, Shenwei Wang wrote: > > > > -----Original Message----- > > From: Greg KH <gregkh@xxxxxxxxxxxxxxxxxxx> > > Sent: Thursday, July 14, 2022 10:24 AM > > To: Shenwei Wang <shenwei.wang@xxxxxxx> > > Cc: linux-serial@xxxxxxxxxxxxxxx > > Subject: Re: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 > > mode > > > > Caution: EXT Email > > > > On Thu, Jul 14, 2022 at 03:11:35PM +0000, Shenwei Wang wrote: > > > > > > > > > > -----Original Message----- > > > > From: Greg KH <gregkh@xxxxxxxxxxxxxxxxxxx> > > > > Sent: Thursday, July 14, 2022 9:31 AM > > > > To: Shenwei Wang <shenwei.wang@xxxxxxx> > > > > Cc: linux-serial@xxxxxxxxxxxxxxx > > > > Subject: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out > > > > parity bit in CS7 mode > > > > > > > > Caution: EXT Email > > > > > > > > On Fri, Jul 08, 2022 at 02:58:00PM -0500, shenwei.wang@xxxxxxx wrote: > > > > > The LPUART hardware doesn't zero out the parity bit on the > > > > > received characters. This behavior won't impact the use cases of > > > > > CS8 because the parity bit is the 9th bit which is not currently used by > > software. > > > > > But the parity bit for CS7 must be zeroed out by software in order > > > > > to get the correct raw data. > > > > > > > > > > Signed-off-by: Shenwei Wang <shenwei.wang@xxxxxxx> > > > > > > > > What commit id does this fix? > > > > > > The issue should have been there since the driver was written. As the CS7 > > mode was rarely used, we didn't notice the problem in the driver before. > > > > So should this be backported to older stable kernels? > > > > Yes, that would be great. Great, properly label it as such when you resend this. thanks, greg k-h
