Hi,
> -----Original Message-----
> From: Doug Anderson <dianders@xxxxxxxxxxxx>
> Sent: Thursday, June 30, 2022 4:45 AM
> To: Vijaya Krishna Nivarthi (Temp) (QUIC) <quic_vnivarth@xxxxxxxxxxx>
> Cc: Andy Gross <agross@xxxxxxxxxx>; bjorn.andersson@xxxxxxxxxx; Konrad
> Dybcio <konrad.dybcio@xxxxxxxxxxxxxx>; Greg Kroah-Hartman
> <gregkh@xxxxxxxxxxxxxxxxxxx>; Jiri Slaby <jirislaby@xxxxxxxxxx>; linux-arm-
> msm <linux-arm-msm@xxxxxxxxxxxxxxx>; linux-serial@xxxxxxxxxxxxxxx; LKML
> <linux-kernel@xxxxxxxxxxxxxxx>; Mukesh Savaliya (QUIC)
> <quic_msavaliy@xxxxxxxxxxx>; Matthias Kaehlcke <mka@xxxxxxxxxxxx>;
> Stephen Boyd <swboyd@xxxxxxxxxxxx>
> Subject: Re: [V2] tty: serial: qcom-geni-serial: Fix get_clk_div_rate() which
> otherwise could return a sub-optimal clock rate.
>
>
>
> > + /* Save the first (lowest freq) within tolerance */
> > + ser_clk = freq;
> > + *clk_div = new_div;
> > + /* no more search for exact match required in 2nd run */
> > + if (!exact_match)
> > + break;
> > + }
> > + }
> >
> > - prev = freq;
> > + div = freq / desired_clk + 1;
>
> Can't you infinite loop now?
>
> Start with:
>
> desired_clk = 10000
> div = 1
> percent_tol = 2
>
>
> Now:
>
> mult = 10000
> offset = 200
> test_freq = 9800
> freq = 9800
> div = 9800 / 10000 + 1 = 0 + 1 = 1
>
> ...and then you'll loop again with "div = 1", won't you? ...or did I get
> something wrong in my analysis? This is the reason my proposed algorithm
> had two loops.
>
>
I went back to your proposed algorithm and made couple of simple changes, and it seemed like what we need.
a) look only for exact match once a clock rate within tolerance is found
b) swap test_freq and freq at end of while loops to make it run as desired
maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
div = 1;
while (div < maxdiv) {
mult = (unsigned long long)div * desired_clk;
if (mult != (unsigned long)mult)
break;
if (ser_clk)
offset = 0;
===================a=====================
else
offset = div_u64(mult * percent_tol, 100);
/*
* Loop requesting (freq - 2%) and possibly (freq).
*
* We'll keep track of the lowest freq inexact match we found
* but always try to find a perfect match. NOTE: this algorithm
* could miss a slightly better freq if there's more than one
* freq between (freq - 2%) and (freq) but (freq) can't be made
* exactly, but that's OK.
*
* This absolutely relies on the fact that the Qualcomm clock
* driver always rounds up.
*/
test_freq = mult - offset;
while (test_freq <= mult) {
freq = clk_round_rate(clk, test_freq);
/*
* A dead-on freq is an insta-win. This implicitly
* handles when "freq == mult"
*/
if (!(freq % desired_clk)) {
*clk_div = freq / desired_clk;
return freq;
}
/*
* Only time clock framework doesn't round up is if
* we're past the max clock rate. We're done searching
* if that's the case.
*/
if (freq < test_freq)
return ser_clk;
/* Save the first (lowest freq) within tolerance */
if (!ser_clk && freq <= mult + offset) {
ser_clk = freq;
*clk_div = div;
}
/*
* If we already rounded up past mult then this will
* cause the loop to exit. If not then this will run
* the loop a second time with exactly mult.
*/
test_freq = max(test_freq + 1, mult);
====b====
}
/*
* freq will always be bigger than mult by at least 1.
* That means we can get the next divider with a DIV_ROUND_UP.
* This has the advantage of skipping by a whole bunch of divs
* If the clock framework already bypassed them.
*/
div = DIV_ROUND_UP(freq, desired_clk);
===b==
}
Will also drop exact_match now.
Will upload v3 after testing.
Thank you,
Vijay/
