Hi Geert, > On Tue, May 3, 2022 at 2:01 PM Phil Edworthy wrote: > > The RZ/V2M SoC has an additional clock to access the registers. The HW > > manual says this clock should not be touched as it is used by the > > "ISP Firmware". > > > > Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx> > > Thanks for your patch! > > > --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml > > +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml > > @@ -9,9 +9,6 @@ title: Renesas EMMA Mobile UART Interface > > maintainers: > > - Magnus Damm <magnus.damm@xxxxxxxxx> > > > > -allOf: > > - - $ref: serial.yaml# > > - > > properties: > > compatible: > > oneOf: > > @@ -29,11 +26,32 @@ properties: > > interrupts: > > maxItems: 1 > > > > - clocks: > > - maxItems: 1 > > +allOf: > > + - $ref: serial.yaml# > > > > - clock-names: > > - const: sclk > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: renesas,r9a09g011-uart > > + then: > > + properties: > > + clocks: > > + items: > > + - description: UART functional clock > > + - description: Optional internal clock to access the > registers > > It's not optional on r9a09g011, right? Right. I'll fix in the next set of patches. > > + clock-names: > > + items: > > + - const: sclk > > + - const: pclk > > + else: > > + properties: > > + clocks: > > + items: > > + - description: UART functional clock > > + clock-names: > > + items: > > + - const: sclk > > > > required: > > - compatible > > The rest LGTM, so with the above fixed: > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> Thanks! Phil
