Hi Phil,
On Wed, Mar 30, 2022 at 5:40 PM Phil Edworthy <phil.edworthy@xxxxxxxxxxx> wrote:
> RZ/V2M has a dual-core Cortex-A53 (1.0 GHz) CPU and built-in AI
> accelerator "DRP-AI" for vision, which is Renesas' original technology.
> It also has a 32-bit LPDDR4 interface and video codec (H.264).
>
> The RZ/V2M is used with ISP firmware that runs on one of the Cortex-A53
> cores. The firmware is an integral part of the SoC such that the HW
> User's Manual documents which of the peripheral modules are used by the
> firmware.
>
> Initial patches enables minimal peripherals on Renesas RZ/V2M EVK board
> and booted via nfs. Ethernet is broadly compatible with the
> etheravb-rcar-gen3 driver, but interrupts need some work so it's not
> been included in this patch set.
>
> Below blocks are enabled on Renesas RZ/V2M EVK board:
> - memory
> - External input clock
> - CPG
> - UART
Thanks for your series!
> v2:
> * Removed SYS dt-bindings patch and corresponding SoC identification
> as we only used the LSI version register. This can be dealt with
> later on.
That patch[1] also introduced the ARCH_R9A09G011 config symbol,
without which none of the new code in this series is built.
[1] [PATCH 07/14] soc: renesas: Identify RZ/V2M SoC
https://lore.kernel.org/all/20220321154232.56315-8-phil.edworthy@xxxxxxxxxxx/
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
