The UART used in these SoCs is actually a variant of the dw apb uart.
Now there is a compatible string in that driver to handle the quirks
switch the compatible for pm_uart over to mstar,msc313-uart.
Signed-off-by: Daniel Palmer <daniel@xxxxxxxx>
---
arch/arm/boot/dts/mstar-v7.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index c26ba9b7b6dd..8464a8f1b136 100644
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -175,7 +175,7 @@ gpio: gpio@207800 {
};
pm_uart: uart@221000 {
- compatible = "ns16550a";
+ compatible = "mstar,msc313-uart", "snps,dw-apb-uart";
reg = <0x221000 0x100>;
reg-shift = <3>;
interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
--
2.35.1
