On 25/01/2022 10:29, Wander Costa wrote:
On Tue, Jan 25, 2022 at 7:06 AM Jon Hunter <jonathanh@xxxxxxxxxx> wrote:
On 25/01/2022 09:36, Jiri Slaby wrote:
...
The test is bogus:
use_fifo = (up->capabilities & UART_CAP_FIFO) &&
port->fifosize > 1 &&
(serial_port_in(port, UART_FCR) & UART_FCR_ENABLE_FIFO)
FCR is write only. Reading it, one gets IIR contents.
In particular, the test is checking whether there is no interrupt
pending (UART_FCR_ENABLE_FIFO == UART_IIR_NO_INT). So it oscillates
between use_fifo and not, depending on the interrupt state of the chip.
Could you change it into something like this:
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -3396,7 +3396,7 @@ void serial8250_console_write(struct
uart_8250_port *up, const char *s,
use_fifo = (up->capabilities & UART_CAP_FIFO) &&
port->fifosize > 1 &&
- (serial_port_in(port, UART_FCR) & UART_FCR_ENABLE_FIFO) &&
+ (up->fcr & UART_FCR_ENABLE_FIFO) &&
/*
* After we put a data in the fifo, the controller will
send
* it regardless of the CTS state. Therefore, only use
fifo
And see whether it fixes the issue. Anyway, of what port type is the
serial port (what says dmesg/setserial about that)?
Thanks. Unfortunately, this did not fix it. The port type is PORT_TEGRA ...
70006000.serial: ttyS0 at MMIO 0x70006000 (irq = 72, base_baud = 25500000) is a Tegra
I see PORT_TEGRA has different values for fifosize and tx_loadsz.
Maybe we should use tx_loadsz.
Could you please give a try to this patch:
diff --git a/drivers/tty/serial/8250/8250_port.c
b/drivers/tty/serial/8250/8250_port.c
index 2abb3de11a48..d3a93e5d55f7 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -3343,7 +3343,7 @@ static void serial8250_console_fifo_write(struct
uart_8250_port *up,
{
int i;
const char *end = s + count;
- unsigned int fifosize = up->port.fifosize;
+ unsigned int fifosize = up->tx_loadsz;
bool cr_sent = false;
while (s != end) {
@@ -3409,8 +3409,8 @@ void serial8250_console_write(struct
uart_8250_port *up, const char *s,
}
use_fifo = (up->capabilities & UART_CAP_FIFO) &&
- port->fifosize > 1 &&
- (serial_port_in(port, UART_FCR) & UART_FCR_ENABLE_FIFO) &&
+ up->tx_loadsz > 1 &&
+ (up->fcr & UART_FCR_ENABLE_FIFO) &&
/*
* After we put a data in the fifo, the controller will send
* it regardless of the CTS state. Therefore, only use fifo
Thanks. Yes that does fix it.
Andy, does this work for X86?
Jon
--
nvpublic
