Hi Kevin,
Thank you very much for your reply.
On 2022/1/20 6:37, Kevin Hilman wrote:
[ EXTERNAL EMAIL ]
Hello,
Yu Tu <yu.tu@xxxxxxxxxxx> writes:
Using the common Clock code to describe the UART baud rate
clock makes it easier for the UART driver to be compatible
with the baud rate requirements of the UART IP on different
meson chips. Add Meson S4 SoC compatible.
Could you describe how this was tested and on which SoCs? There seem to
be some changes in this series that might affect previous SoCs.
For me, the board starts normally and prints. My intention was to add
the S4 SOC UART compatible, but for the S4 our baud rate clock is
calculated at 12MHz by default.So a series of changes were made at your
suggestion.
Since most SoCs are too old, I was able to find all the platforms myself
such as Meson6, Meson8, Meson8b, GXL and so on. I only tested it with
G12A and S4.But when I talked to Martin earlier he tried meson8b's log.
The test patch is in the attachment.
I have found that on some boards with this change, the initcall_debug
Uart driver takes longer to initialize. Running the stty command to
change the baud rate at the same time may cause a jam.
I'd love to know what else you suggest.
Thanks,
Kevin
# cat /sys/kernel/debug/clk//clk_summary | head
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
xtal 6 6 0 24000000 0 0 50000 Y
ff803000.serial#xtal_div 1 1 0 12000000 0 0 50000 Y
ff803000.serial#use_xtal 1 1 0 12000000 0 0 50000 Y
ff803000.serial#baud_div 1 1 0 115385 0 0 50000 Y
cts_oscin 0 0 0 24000000 0 0 50000 Y
g12a_ao_cec_pre 0 0 0 24000000 0 0 50000 N
g12a_ao_cec_div 0 0 0 32742 0 0 50000 Y
# cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
[...]
xtal 6 6 2 24000000 0 0 50000 Y
[...]
c81004c0.serial#xtal_div3 0 0 0 8000000 0 0 50000 Y
[...]
fixed_pll_dco 1 1 0 2550000000 0 0 50000 Y
fixed_pll 1 1 0 2550000000 0 0 50000 Y
[...]
fclk_div3_div 1 1 0 850000000 0 0 50000 Y
fclk_div3 2 2 0 850000000 0 0 50000 Y
[...]
mpeg_clk_sel 1 1 0 850000000 0 0 50000 Y
mpeg_clk_div 1 1 0 141666667 0 0 50000 Y
clk81 17 20 0 141666667 0 0 50000 Y
[...]
c81004c0.serial#clk81_div4 1 1 0 35416666 0 0 50000 Y
c81004c0.serial#use_xtal 1 1 0 35416666 0 0 50000 Y
c81004c0.serial#baud_div 1 1 0 115364 0 0 50000 Y
# cat /sys/kernel/debug/clk/clk_summary | head
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
xtal 7 7 0 24000000 0 0 50000 Y
fe07a000.serial#xtal_div 1 1 0 12000000 0 0 50000 Y
fe07a000.serial#use_xtal 1 1 0 12000000 0 0 50000 Y
fe07a000.serial#baud_div 1 1 0 923077 0 0 50000 Y
hdcp22_skpclk_mux 0 0 0 24000000 0 0 50000 Y
hdcp22_skpclk_div 0 0 0 24000000 0 0 50000 Y
hdcp22_skpclk_gate 0 0 0 24000000 0 0 50000 N
