The control register is a writeonly register that's why reading it doesn't make any sense. The manual states "This is a write-only register. Issuing a read request to the control register generates the read acknowledgment with zero data." Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxxxxx> --- v2: Update the description https://www.xilinx.com/support/documentation/ip_documentation/axi_uartlite/v2_0/pg142-axi-uartlite.pdf drivers/tty/serial/uartlite.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c index dfc1ba4e1572..0df471eddb0e 100644 --- a/drivers/tty/serial/uartlite.c +++ b/drivers/tty/serial/uartlite.c @@ -297,7 +297,6 @@ static void ulite_shutdown(struct uart_port *port) struct uartlite_data *pdata = port->private_data; uart_out32(0, ULITE_CONTROL, port); - uart_in32(ULITE_CONTROL, port); /* dummy */ free_irq(port->irq, port); clk_disable(pdata->clk); } @@ -368,7 +367,6 @@ static int ulite_request_port(struct uart_port *port) } pdata->reg_ops = &uartlite_be; - ret = uart_in32(ULITE_CONTROL, port); uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port); ret = uart_in32(ULITE_STATUS, port); /* Endianess detection */ -- 2.17.1
