On Tue, Nov 2, 2021 at 5:12 PM Emil Renner Berthing <kernel@xxxxxxxx> wrote: > Add bindings for the GPIO/pin controller on the JH7100 RISC-V SoC by > StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. > > Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx> > --- > > @Linus: I'm really struggling to find a good way to describe how pin > muxing works on the JH7100. As you can see I've now resorted to > ascii-art to try to explain it, but please let me know if it's still > unclear. This looks perfectly acceptable to me: Reviewed-by: Linus Walleij <linus.walleij@xxxxxxxxxx> As it appears to have some cross dependencies I assume it will be merged through the SoC tree? Yours, Linus Walleij
