On Tue, Oct 12, 2021 at 4:43 PM Emil Renner Berthing <kernel@xxxxxxxx> wrote:
>
> On the StarFive JH7100 SoC the uart core clocks can't be set to exactly
> 16 * 115200Hz and many other common bitrates. Trying this will only
> result in a higher input clock, but low enough that the uart's internal
> divisor can't come close enough to the baud rate target. So rather than
> try to set the input clock it's better to rely solely on the uart's
> internal divisor.
s/uart/UART/g
...
> unsigned int skip_autocfg:1;
> unsigned int uart_16550_compatible:1;
> + unsigned int skip_clk_set_rate:1;
Keep skip_* bitfields grouped.
...
> + if (!d->skip_clk_set_rate) {
I believe you have to rebase this patch on top of tty/tty-next.
Besides that, please, avoid indentation changes, i.e. refactor your
patch accordgingly.
> }
--
With Best Regards,
Andy Shevchenko
