On 04/08/2021 16:39, Sam Protsenko wrote:
> Hi Marc,
>
> On Fri, 30 Jul 2021 at 19:50, Marc Zyngier <maz@xxxxxxxxxx> wrote:
>>
>> On 2021-07-30 15:49, Sam Protsenko wrote:
>>> Samsung Exynos850 is ARMv8-based mobile-oriented SoC.
>>>
>>> Features:
>>> * CPU: Cortex-A55 Octa (8 cores), up to 2 GHz
>>> * Memory interface: LPDDR4/4x 2 channels (12.8 GB/s)
>>> * SD/MMC: SD 3.0, eMMC5.1 DDR 8-bit
>>> * Modem: 4G LTE, 3G, GSM/GPRS/EDGE
>>> * RF: Quad GNSS, WiFi 5 (802.11ac), Bluetooth 5.0
>>> * GPU: Mali-G52 MP1
>>> * Codec: 1080p 60fps H64, HEVC, JPEG HW Codec
>>> * Display: Full HD+ (2520x1080)@60fps LCD
>>> * Camera: 16+5MP/13+8MP ISP, MIPI CSI 4/4/2, FD, DRC
>>> * Connectivity: USB 2.0 DRD, USI (SPI/UART/I2C), HSI2C, I3C, ADC,
>>> Audio
>>>
>>> This patch adds minimal SoC support. Particular board device tree files
>>> can include exynos850.dtsi file to get SoC related nodes, and then
>>> reference those nodes further as needed.
>>>
>>> Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
>>> ---
>>> .../boot/dts/exynos/exynos850-pinctrl.dtsi | 782 ++++++++++++++++++
>>> arch/arm64/boot/dts/exynos/exynos850-usi.dtsi | 30 +
>>> arch/arm64/boot/dts/exynos/exynos850.dtsi | 245 ++++++
>>> 3 files changed, 1057 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
>>> create mode 100644 arch/arm64/boot/dts/exynos/exynos850-usi.dtsi
>>> create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
>>> b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
>>> new file mode 100644
>>> index 000000000000..4cf0a22cc6db
>>
>> [...]
>>
>>> + gic: interrupt-controller@12a00000 {
>>> + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>>
>> One thing for sure, it cannot be both. And given that it is
>> an A55-based SoC, it isn't either. It is more likely a GIC400.
>>
>
> Yes, it's GIC-400, thanks for pointing that out. Will fix that in v2.
>
>>> + #interrupt-cells = <3>;
>>> + #address-cells = <0>;
>>> + interrupt-controller;
>>> + reg = <0x0 0x12a01000 0x1000>,
>>> + <0x0 0x12a02000 0x1000>,
>>
>> This is wrong. It is architecturally set to 8kB.
>>
>
> Nice catch! Actually there is an error (typo?) in SoC's TRM, saying
> that Virtual Interface Control Register starts at 0x3000 offset (from
> 0x12a00000), where it obviously should be 0x4000, that's probably
> where this dts error originates from. Btw, I'm also seeing the same
> error in exynos7.dtsi.
What's the error exactly? The "Virtual interface control register"
offset (3rd region) is set properly to 0x4000 on Exynos7. Also one for
the Exynos5433 looks correct.
> Though I don't have a TRM for Exynos7 SoCs, so
> not sure if I should go ahead and fix that too. Anyway, for Exynos850,
> I'll fix that in v2 series.
However while we are at addresses - why are you using address-cells 2?
It adds everywhere additional 0x0 before actual address.
Best regards,
Krzysztof
