On Thu, Jun 03, 2021 at 07:03:25AM +0000, Raviteja Narayanam wrote: > Hi, > > The uart peripheral on Xilinx Versal platform is ARM primecell. > Our environment is 32-bit access type but the ARM primecell uart in pl011 driver has default 16 bit access type. > (https://github.com/torvalds/linux/blob/master/drivers/tty/serial/amba-pl011.c#L2665 access_32b is false for 'vendor_arm') > This is causing asynchronous abort on our platform when any UART register is written from the pl011 driver. > > Need suggestion on how we can address this issue and if the below approach is fine. > > As this is platform specific issue, we can have a new device tree property (memory_access_type), specifying the 32 bit type. > In the probe function, override the behavior (uap->port.iotype) if this property is present in DT. > In this way, we can have support for our SOC, without breaking any legacy ones. There is no other way to determine what this device is other than platform data? Why not just set the vendor id in your device to a new one and provide a correct setting in that new vendor data structure, like all other devices for this chip have done before? If it is the same id, and works differently, then that is a hardware issue that you need to take up with your hardware designers to get fixed as that is obviously a problem. thanks, greg k-h
