Hi Mateusz, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on robh/for-next] [also build test WARNING on tty/tty-testing usb/usb-testing staging/staging-testing driver-core/driver-core-testing linus/master v5.8-rc6 next-20200724] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Mateusz-Holenko/LiteX-SoC-controller-and-LiteUART-serial-driver/20200722-183024 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next config: arc-randconfig-s032-20200726 (attached as .config) compiler: arc-elf-gcc (GCC) 9.3.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # apt-get install sparse # sparse version: v0.6.2-93-g4c6cbe55-dirty # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=arc If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@xxxxxxxxx> sparse warnings: (new ones prefixed by >>) >> drivers/soc/litex/litex_soc_ctrl.c:61:17: sparse: sparse: cast from restricted __le32 >> drivers/soc/litex/litex_soc_ctrl.c:61:17: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [usertype] val @@ got restricted __le32 [usertype] @@ >> drivers/soc/litex/litex_soc_ctrl.c:61:17: sparse: expected unsigned int [usertype] val drivers/soc/litex/litex_soc_ctrl.c:61:17: sparse: got restricted __le32 [usertype] >> drivers/soc/litex/litex_soc_ctrl.c:61:17: sparse: sparse: cast from restricted __le32 >> drivers/soc/litex/litex_soc_ctrl.c:61:17: sparse: sparse: cast from restricted __le32 >> drivers/soc/litex/litex_soc_ctrl.c:61:17: sparse: sparse: cast from restricted __le32 >> drivers/soc/litex/litex_soc_ctrl.c:61:17: sparse: sparse: cast from restricted __le32 drivers/soc/litex/litex_soc_ctrl.c:77:32: sparse: sparse: cast to restricted __le32 drivers/soc/litex/litex_soc_ctrl.c:77:32: sparse: sparse: cast to restricted __le32 drivers/soc/litex/litex_soc_ctrl.c:77:32: sparse: sparse: cast to restricted __le32 drivers/soc/litex/litex_soc_ctrl.c:77:32: sparse: sparse: cast to restricted __le32 drivers/soc/litex/litex_soc_ctrl.c:77:32: sparse: sparse: cast to restricted __le32 drivers/soc/litex/litex_soc_ctrl.c:77:32: sparse: sparse: cast to restricted __le32 vim +61 drivers/soc/litex/litex_soc_ctrl.c 32 33 /* 34 * LiteX SoC Generator, depending on the configuration, 35 * can split a single logical CSR (Control & Status Register) 36 * into a series of consecutive physical registers. 37 * 38 * For example, in the configuration with 8-bit CSR Bus, 39 * 32-bit aligned (the default one for 32-bit CPUs) a 32-bit 40 * logical CSR will be generated as four 32-bit physical registers, 41 * each one containing one byte of meaningful data. 42 * 43 * For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus 44 * 45 * The purpose of `litex_set_reg`/`litex_get_reg` is to implement 46 * the logic of writing to/reading from the LiteX CSR in a single 47 * place that can be then reused by all LiteX drivers. 48 */ 49 void litex_set_reg(void __iomem *reg, unsigned long reg_size, 50 unsigned long val) 51 { 52 unsigned long shifted_data, shift, i; 53 unsigned long flags; 54 55 spin_lock_irqsave(&csr_lock, flags); 56 57 for (i = 0; i < reg_size; ++i) { 58 shift = ((reg_size - i - 1) * LITEX_SUBREG_SIZE_BIT); 59 shifted_data = val >> shift; 60 > 61 writel(cpu_to_le32(shifted_data), reg + (LITEX_REG_SIZE * i)); 62 } 63 64 spin_unlock_irqrestore(&csr_lock, flags); 65 } 66 EXPORT_SYMBOL_GPL(litex_set_reg); 67 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
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