On Mon, Feb 10, 2020 at 2:50 PM Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx> wrote: > > Hello George, > > On Mon, Feb 10, 2020 at 01:29:49PM -0600, George Hilliard wrote: > > @@ -1390,6 +1392,8 @@ static int imx_uart_startup(struct uart_port *port) > > ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN; > > if (!sport->dma_is_enabled) > > ucr4 |= UCR4_OREN; > > + if (sport->inverted_rx) > > + ucr4 |= UCR4_INVR; > > You fail to clear this bit if .inverted_rx is false. I believe this is taken care of by the SRST asserted slightly above this - UCR* is reset by this. I see that this reset is also done in the imx_uart_flush_buffer() implementation, but as I understand it, this is a cleanup method that doesn't reconfigure much of the peripheral. > > imx_uart_writel(sport, ucr4, UCR4); > > > > ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; > > @@ -1404,19 +1408,17 @@ static int imx_uart_startup(struct uart_port *port) > > ucr2 &= ~UCR2_RTSEN; > > imx_uart_writel(sport, ucr2, UCR2); > > > > + ucr3 = imx_uart_readl(sport, UCR3); > > + if (sport->inverted_tx) > > + ucr3 |= UCR3_INVT; > > Also I think setting this bit here is a bit late because UCR2_TXEN was > already set so changing UCR3_INVT probably results in a spike?! Good point here; this should indeed be done before TX start. George
