For Synopsys DesignWare 8250 uart which version >= 4.00a, there's a
valid divisor latch fraction register.
Now the preparation is done, it's easy to add the feature support.
This patch firstly tries to get the fractional divisor width during
probe, then setups specific get_divisor() and set_divisor() hook.
Among other changes the FIFO size is now retrieved from the hardware.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
---
drivers/tty/serial/8250/8250_lpss.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_lpss.c b/drivers/tty/serial/8250/8250_lpss.c
index 3bf23770c188..0c6aa990db3d 100644
--- a/drivers/tty/serial/8250/8250_lpss.c
+++ b/drivers/tty/serial/8250/8250_lpss.c
@@ -113,7 +113,6 @@ static unsigned int byt_get_mctrl(struct uart_port *port)
static int byt_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
{
struct dw_dma_slave *param = &lpss->dma_param;
- struct uart_8250_port *up = up_to_u8250p(port);
struct pci_dev *pdev = to_pci_dev(port->dev);
unsigned int dma_devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
struct pci_dev *dma_dev = pci_get_slot(pdev->bus, dma_devfn);
@@ -139,10 +138,6 @@ static int byt_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
param->m_master = 0;
param->p_master = 1;
- /* TODO: Detect FIFO size automaticaly for DesignWare 8250 */
- port->fifosize = 64;
- up->tx_loadsz = 64;
-
lpss->dma_maxburst = 16;
port->set_termios = byt_set_termios;
@@ -316,6 +311,8 @@ static int lpss8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (ret)
return ret;
+ dw8250_setup_port(&uart.port);
+
ret = lpss8250_dma_setup(lpss, &uart);
if (ret)
goto err_exit;
--
2.20.1
