On Tue, Sep 18, 2018 at 09:35:12AM -0700, Vinod wrote: > On 01-09-18, 22:12, Manivannan Sadhasivam wrote: > > > @@ -364,6 +372,26 @@ static inline int owl_dma_cfg_lli(struct owl_dma_vchan *vchan, > > OWL_DMA_MODE_DT_DCU | OWL_DMA_MODE_SAM_INC | > > OWL_DMA_MODE_DAM_INC; > > > > + break; > > + case DMA_MEM_TO_DEV: > > + mode |= OWL_DMA_MODE_TS(vchan->drq) > > + | OWL_DMA_MODE_ST_DCU | OWL_DMA_MODE_DT_DEV > > + | OWL_DMA_MODE_SAM_INC | OWL_DMA_MODE_DAM_CONST; > > + > > + /* Handle bus width for UART */ > > + if (sconfig->dst_addr_width == DMA_SLAVE_BUSWIDTH_1_BYTE) > > + mode |= OWL_DMA_MODE_NDDBW_8BIT; > > this is fine per se, but not correct way to handle in dmaengine driver. > You should be agnostic to user of dmaengine, so handle all the buswidths > the IP block supports and update the values accordingly. That way new > uses can be added w/o requiring change in dmaengine driver > Hi Vinod, Currently, all members of Owl family supports only 32bit and 8bit bus widths. 32bit is common for all peripherals and 8bit applies to only UART since the internal buffer is 8bit wide. So, this makes sense to me! Thanks, Mani > -- > ~Vinod
