Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers.
Use the register area size to determine the spacing between register.
Signed-off-by: Chris Brandt <chris.brandt@xxxxxxxxxxx>
---
drivers/tty/serial/sh-sci.c | 22 +++++++++++++---------
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 6ff6f2bf3b9b..138296ec9a7d 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -348,15 +348,15 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
[SCIx_SH4_SCIF_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 16 },
- [SCBRR] = { 0x04, 8 },
- [SCSCR] = { 0x08, 16 },
- [SCxTDR] = { 0x0c, 8 },
- [SCxSR] = { 0x10, 16 },
- [SCxRDR] = { 0x14, 8 },
- [SCFCR] = { 0x18, 16 },
- [SCFDR] = { 0x1c, 16 },
- [SCSPTR] = { 0x20, 16 },
- [SCLSR] = { 0x24, 16 },
+ [SCBRR] = { 0x02, 8 },
+ [SCSCR] = { 0x04, 16 },
+ [SCxTDR] = { 0x06, 8 },
+ [SCxSR] = { 0x08, 16 },
+ [SCxRDR] = { 0x0a, 8 },
+ [SCFCR] = { 0x0c, 16 },
+ [SCFDR] = { 0x0e, 16 },
+ [SCSPTR] = { 0x10, 16 },
+ [SCLSR] = { 0x12, 16 },
},
.fifosize = 16,
.overrun_reg = SCLSR,
@@ -2939,6 +2939,10 @@ static int sci_init_single(struct platform_device *dev,
port->regshift = 1;
}
+ if (p->regtype == SCIx_SH4_SCIF_REGTYPE)
+ if (sci_port->reg_size >= 0x20)
+ port->regshift = 1;
+
/*
* The UART port needs an IRQ value, so we peg this to the RX IRQ
* for the multi-IRQ ports, which is where we are primarily
--
2.16.1
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