On Mon, 2018-06-04 at 13:50 +0200, Giulio Benetti wrote: > Hi, > > Il 04/06/2018 13:38, Andy Shevchenko ha scritto: > > On Mon, 2018-06-04 at 12:50 +0200, Giulio Benetti wrote: > > > Hi, > > > > > > Il 04/06/2018 12:17, Andy Shevchenko ha scritto: > > > > On Fri, 2018-06-01 at 14:40 +0200, Giulio Benetti wrote: > > > > > Some 8250 ports only have TEMT interrupt, so current > > > > > implementation > > > > > can't work for ports without it. The only chance to make it > > > > > work > > > > > is to > > > > > loop-read on LSR register. > > > > > > > > > > With NO TEMT interrupt check if both TEMT and THRE are set > > > > > looping > > > > > on > > > > > LSR register. > > > > > --- a/drivers/tty/serial/8250/8250_dw.c > > > > > +++ b/drivers/tty/serial/8250/8250_dw.c > > > > > - int ret = serial8250_em485_init(up); > > > > > + int ret = serial8250_em485_init(up, false); > > > > > > > > Is true for all possible DW configured types? Or it's your > > > > particular > > > > case? > > > > > > > > > > I've checked on Synopsis Designware 8250 datasheet and it's not > > > supported. > > > Here is datasheet I went through: > > > https://linux-sunxi.org/images/d/d2/Dw_apb_uart_db.pdf > > > > > > There seems not to be TEMT interrupt, I use it under sunxi SoC and > > > on > > > their datasheet(A20 for example), they don't report that interrupt > > > too. > > > So it seems to be valid for all DW configured types, anyway I > > > don't > > > know > > > how many IP reviews there could be of that peripheral. > > > > This is an excerpt from the document you referred to: > > > > --- 8< --- 8< --- > > > > 6 TEMT R Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) > > and > > FIFOs enabled (FCR[0] set to one), this bit is set whenever the > > Transmitter Shift Register and the FIFO are both empty. If in non- > > FIFO > > mode or FIFOs are disabled, this bit is set whenever the Transmitter > > Holding Register and the Transmitter Shift Register are both empty. > > > > Reset Value: 0x1 > > > > --- 8< --- 8< --- > > > > > > If I'm reading this correctly the support is there. Or otherwise, > > care > > to point exact paragraph needs to be read and checked? > > In the beginning I thought the same as you but > unfortunately LSR is only a status register and IER doesn't have > corresponding TEMT bit to enable an interrupt on TEMT triggering. > On OMAP instead there is a specific interrupt bound to TEMT LSR flag. > And THRE interrupt is not enough because shift register won't be > empty > when it triggers, so you would loose some bit of last byte to be > transmitted. Hmm... Okay, it's something you and Matwey better to discuss. P.S. Latest version of document I have does describe RS485 HW supported mode. I don't know if it was added recently to the IP itself, or just missed documentation. That's what you need to clarify with Synopsys. -- Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> Intel Finland Oy -- To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
