On Wed, Jan 25, 2017 at 5:07 PM, Uwe Kleine-König
<u.kleine-koenig@xxxxxxxxxxxxxx> wrote:
>> static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
>> {
>> - *ucr2 &= ~UCR2_CTSC;
>> - *ucr2 |= UCR2_CTS;
>> + *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
>>
>> mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
>> }
>>
>> static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
>> {
>> - *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
>> + *ucr2 &= ~UCR2_CTSC;
>> + *ucr2 |= UCR2_CTS;
>>
>> mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
>> }
>
> I think the above is wrong. Setting CTS makes the CTS pin low (active).
> So AFAICT (that is without testing) drop this hunk.
I think the reference manual make confusion when they say active and inactive.
Active and inactive state depends on the SER_RS485_RTS_ON_SEND and
SER_RS485_RTS_AFTER_SEND flags.
Let's give this example:
Userspace configures the uart port as follows:
/* enable RS485 mode: */
rs485conf.flags |= SER_RS485_ENABLED;
/* set logical level for RTS pin equal to 1 when sending: */
rs485conf.flags |= SER_RS485_RTS_ON_SEND;
/* set logical level for RTS pin equal to 0 after sending: */
rs485conf.flags &= ~(SER_RS485_RTS_AFTER_SEND);
, which would translate in our imx_port_rts_active():
1. In the case of using the native CTS pin:
- clear CTSC and set CTS, so that The CTS_B pin is high.
2. In the case of using CTS as a GPIO pin:
- It will set the GPIO as high.
So the patch does the correct logic now.
> Please compare the level of the CTS pin you see with the rts-gpio. Do
> they match (logically) given that RTS is active low?
Yes, that's what I did: I can see CTS pin going to 1 during TX and
going to 0 during RX.
Maybe Clemens could help testing the native CTS case on his board with
this patch?
Thanks
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