This patch replaces the setup flags for EXAR tty pci chips (XR17V35x) setting
the GPIO pin direction from OUTPUT (0x00) to INPUT (0xff) which is is actually
the default register value on chip reset.
Chip default GPIO state 'INPUT' is the "safe" option, since it
dont switch any outputs on reset/powerup. So the driver should not do either.
Signed-off-by: Dieter Hilfer <dieter.hilfer@xxxxxxxxxx>
Reviewed-by: Soeren Grunewald <soeren.grunewald@xxxxxxx>
---
drivers/tty/serial/8250/8250_pci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
index 98862aa..5b2a5a3 100644
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -1772,13 +1772,13 @@ pci_xr17v35x_setup(struct serial_private *priv,
writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
- writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
+ writeb(0xff, p + 0x93); /*MPIOSEL[7:0]*/
writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
- writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
+ writeb(0xff, p + 0x99); /*MPIOSEL[15:8]*/
writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
}
writeb(0x00, p + UART_EXAR_8XMODE);
--
1.9.1
--
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