>Среда, 8 июня 2016, 19:39 +03:00 от Peter Hurley <peter@xxxxxxxxxxxxxxxxxx>:
>
>Hi Alexander,
>
>On 06/07/2016 08:59 AM, Alexander Shiyan wrote:
>> The patch adds a barrier between two sequential read/write cycles
>> to provide the required minimum High-CS time.
>
>Which is how long? 100ns?
>The commit log should include this information.
...
>I'm wondering if this delay should be implemented in the
>i/o accessors instead. Otherwise, the delay may be skipped; eg.,
>sccnxp_start_tx(), sccnxp_handle_rx(), sccnxp_handle_events(), ...
>
>
>> +static inline void sccnxp_barrier(void)
>> +{
>> +/* Barrier between read and/or write cycles */
>> +cpu_relax();
>
>ndelay(100 /* ns */);
...
>Note 7 on pg 19 of the 2698 datasheet [1] says:
>
>"Consecutive write operations to the command register require at least three
>edges of the X1 clock between writes"
>
>By my math, that should be 360ns. Agree?
>
>Regards,
>Peter Hurley
>
>[1] http://www.nxp.com/documents/data_sheet/SCC2698B.pdf
Hello.
You talk about SCC2698, this chip is not defined in the driver source,
but if it compatible, this is not a problem.
Yes, I mean tRWD parameter, i.e. HIGH time between read and/or write cycles
(as defined in SC28L92 datasheet). This is 17ns minimum for SC28L92, so should I
introduce one more internal parameter to specify this value for each supported chip?
In fact, one "barrier()" is enough, but we can make this better :)
PS: http://www.nxp.com/documents/data_sheet/SC28L92.pdf
Thanks.
---
��.n��������+%������w��{.n�����{��ǫ����{ay� ʇڙ���f���h������_�(�階�ݢj"��������G����?���&��
