Re: [PATCH 5/6] serial: 8250: Extract IIR logic steering from rx dma

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On 04/12/2016 10:11 AM, Sebastian Andrzej Siewior wrote:
> On 04/12/2016 06:19 PM, Peter Hurley wrote:
>> Well, the UART_IIR_RDI comment is wrong so I didn't want to preserve that,
>> and the UART_IIR_RX_TIMEOUT is the same thing that happens with the
>> base 8250 dma handling as well, so I didn't see the point.
>>
>> The UART_IIR_RDI interrupt happens because:
>>
>> 1) The programmed DMA transfer has completed
>> 2) But the DMA completion handler hasn't run yet because the virt-dma
>>    tasklet hasn't run yet because of the softirq priority inversion
>>    http://www.gossamer-threads.com/lists/engine?do=post_view_flat;post=2381467;page=1;sb=post_latest_reply;so=ASC;mh=25;list=linux
>> 3) in the meantime, data has continued to arrive until the fifo is refilled
>>    which triggers the UART_IIR_RDI
>>
>> Which is ironic because the UART_IIR_RDI is normally what we want to
>> actually happen because that is the dma transaction flow expected by
>> the base 8250 dma handling.
> 
> Not on TI's hardware I had :)

Maybe with sdma only?


> I assure you that if you have 30 Bytes in the FIFO and program a
> transfer for 48 Bytes now (i.e. ignore the softirq thingy) then the TI
> HW will count for 48 bytes from *now* even if it would only need 18
> additional bytes to start the transfer. That is why the transfer is
> programmed ASAP because if the FIFO is filled with less than 16 bytes
> you have chance for a 48bytes transfer to happen.

This has never been observed with edma.

The only time that UART_IIR_RDI was asserted was for dma completion
latencies ~300us+ ( < 10 times in 198000 rx dma transfers).
In every case, the rx dma was already completed (descriptor had been
retired) but the completion handler had not run yet.

If what you say would be true, then 100s of UART_IIR_RDI
interrupts would occur because softirq latencies are commonly
> 20us (> 6 frames at 3Mbaud).
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