On 04/12/2016 06:19 PM, Peter Hurley wrote: > Well, the UART_IIR_RDI comment is wrong so I didn't want to preserve that, > and the UART_IIR_RX_TIMEOUT is the same thing that happens with the > base 8250 dma handling as well, so I didn't see the point. > > The UART_IIR_RDI interrupt happens because: > > 1) The programmed DMA transfer has completed > 2) But the DMA completion handler hasn't run yet because the virt-dma > tasklet hasn't run yet because of the softirq priority inversion > http://www.gossamer-threads.com/lists/engine?do=post_view_flat;post=2381467;page=1;sb=post_latest_reply;so=ASC;mh=25;list=linux > 3) in the meantime, data has continued to arrive until the fifo is refilled > which triggers the UART_IIR_RDI > > Which is ironic because the UART_IIR_RDI is normally what we want to > actually happen because that is the dma transaction flow expected by > the base 8250 dma handling. Not on TI's hardware I had :) I assure you that if you have 30 Bytes in the FIFO and program a transfer for 48 Bytes now (i.e. ignore the softirq thingy) then the TI HW will count for 48 bytes from *now* even if it would only need 18 additional bytes to start the transfer. That is why the transfer is programmed ASAP because if the FIFO is filled with less than 16 bytes you have chance for a 48bytes transfer to happen. Sebastian -- To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
