Hi,
On Wed, Aug 05, 2015 at 05:54:11PM +0800, Qipeng Zha wrote:
> This patch is to revert below workaround patch
> 33acbb82695f ("serial: 8250_dw: Report CTS asserted for auto flow")
>
> Since Designware 8250 controller can manage flow control automatically,
> and serial core support auto CTS mode, so it's better to just enable
> auto CTS mode for this controller to solve issue reported in workaround
> patch.
Tim, this is reverting your patch so can you take a look at it.
Thanks,
> Signed-off-by: Huiquan Zhong <huiquan.zhong@xxxxxxxxx>
> Signed-off-by: Qipeng Zha <qipeng.zha@xxxxxxxxx>
>
> ---
> change in V2:
> update subject line and commit message.
> ---
> drivers/tty/serial/8250/8250_dw.c | 22 ----------------------
> 1 file changed, 22 deletions(-)
>
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index f78afeb..1f15cb1 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -57,7 +57,6 @@
>
> struct dw8250_data {
> u8 usr_reg;
> - int last_mcr;
> int line;
> int msr_mask_on;
> int msr_mask_off;
> @@ -77,12 +76,6 @@ static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
> {
> struct dw8250_data *d = p->private_data;
>
> - /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
> - if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
> - value |= UART_MSR_CTS;
> - value &= ~UART_MSR_DCTS;
> - }
> -
> /* Override any modem control signals if needed */
> if (offset == UART_MSR) {
> value |= d->msr_mask_on;
> @@ -102,11 +95,6 @@ static void dw8250_force_idle(struct uart_port *p)
>
> static void dw8250_serial_out(struct uart_port *p, int offset, int value)
> {
> - struct dw8250_data *d = p->private_data;
> -
> - if (offset == UART_MCR)
> - d->last_mcr = value;
> -
> writeb(value, p->membase + (offset << p->regshift));
>
> /* Make sure LCR write wasn't ignored */
> @@ -145,11 +133,6 @@ static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
>
> static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
> {
> - struct dw8250_data *d = p->private_data;
> -
> - if (offset == UART_MCR)
> - d->last_mcr = value;
> -
> value &= 0xff;
> __raw_writeq(value, p->membase + (offset << p->regshift));
> /* Read back to ensure register write ordering. */
> @@ -176,11 +159,6 @@ static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
>
> static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
> {
> - struct dw8250_data *d = p->private_data;
> -
> - if (offset == UART_MCR)
> - d->last_mcr = value;
> -
> writel(value, p->membase + (offset << p->regshift));
>
> /* Make sure LCR write wasn't ignored */
--
heikki
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