On Mon, 2015-03-09 at 19:07 +0200, Andy Shevchenko wrote:
> Intel Tangier contains 4 HSUART ports as found on Intel Edison board which are
> 8250 compatible. The patch adds necessary bits to the driver.
This one will be resent later based on serial8250_get_ps() helper.
>
> Note that the HSU port0 is currently unavailable and thus not supported.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
> ---
> drivers/tty/serial/8250/8250_pci.c | 90 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 90 insertions(+)
>
> diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
> index 11784e9..4036e8b 100644
> --- a/drivers/tty/serial/8250/8250_pci.c
> +++ b/drivers/tty/serial/8250/8250_pci.c
> @@ -1528,6 +1528,55 @@ byt_serial_setup(struct serial_private *priv,
>
> #define INTEL_MID_UART_PS 0x30
> #define INTEL_MID_UART_MUL 0x34
> +#define INTEL_MID_UART_DIV 0x38
> +
> +static void intel_mid_set_termios_38_4M(struct uart_port *p,
> + struct ktermios *termios,
> + struct ktermios *old)
> +{
> + unsigned int baud = tty_termios_baud_rate(termios);
> + u32 ps, mul, div;
> +
> + ps = 0x0a;
> +
> + switch (baud) {
> + case 500000:
> + case 1000000:
> + case 1500000:
> + case 3000000:
> + mul = 0x19;
> + div = 0x20;
> + p->uartclk = 48000000;
> + break;
> + case 2000000:
> + case 4000000:
> + mul = 0x05;
> + div = 0x06;
> + ps = 0x08;
> + p->uartclk = 64000000;
> + break;
> + case 2500000:
> + mul = 0x7d;
> + div = 0xc0;
> + p->uartclk = 40000000;
> + break;
> + case 3500000:
> + mul = 0xaf;
> + div = 0xc0;
> + p->uartclk = 56000000;
> + break;
> + default:
> + mul = 0x18;
> + div = 0x19;
> + p->uartclk = 58982400;
> + }
> +
> + writel(ps, p->membase + INTEL_MID_UART_PS);
> + writel(mul, p->membase + INTEL_MID_UART_MUL);
> + writel(div, p->membase + INTEL_MID_UART_DIV);
> +
> + serial8250_do_set_termios(p, termios, old);
> +}
>
> static void intel_mid_set_termios_50M(struct uart_port *p,
> struct ktermios *termios,
> @@ -1668,6 +1717,27 @@ static int pnw_serial_setup(struct serial_private *priv,
> return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
> }
>
> +#define PCI_DEVICE_ID_INTEL_TNG_UART 0x1191
> +
> +static int tng_serial_setup(struct serial_private *priv,
> + const struct pciserial_board *board,
> + struct uart_8250_port *port, int idx)
> +{
> + struct pci_dev *pdev = priv->dev;
> + struct pci_dev *dma_dev;
> + int index = PCI_FUNC(pdev->devfn);
> +
> + /* Currently no support for HSU port0 */
> + if (index-- == 0)
> + return -ENODEV;
> +
> + dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0));
> +
> + port->port.set_termios = intel_mid_set_termios_38_4M;
> +
> + return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
> +}
> +
> static int
> pci_omegapci_setup(struct serial_private *priv,
> const struct pciserial_board *board,
> @@ -2153,6 +2223,13 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
> },
> {
> .vendor = PCI_VENDOR_ID_INTEL,
> + .device = PCI_DEVICE_ID_INTEL_TNG_UART,
> + .subvendor = PCI_ANY_ID,
> + .subdevice = PCI_ANY_ID,
> + .setup = tng_serial_setup,
> + },
> + {
> + .vendor = PCI_VENDOR_ID_INTEL,
> .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
> .subvendor = PCI_ANY_ID,
> .subdevice = PCI_ANY_ID,
> @@ -3029,6 +3106,7 @@ enum pci_board_num_t {
> pbn_ce4100_1_115200,
> pbn_byt,
> pbn_pnw,
> + pbn_tng,
> pbn_qrk,
> pbn_omegapci,
> pbn_NETMOS9900_2s_115200,
> @@ -3800,6 +3878,11 @@ static struct pciserial_board pci_boards[] = {
> .num_ports = 1,
> .base_baud = 115200,
> },
> + [pbn_tng] = {
> + .flags = FL_BASE0,
> + .num_ports = 1,
> + .base_baud = 1843200,
> + },
> [pbn_qrk] = {
> .flags = FL_BASE0,
> .num_ports = 1,
> @@ -5546,6 +5629,13 @@ static struct pci_device_id serial_pci_tbl[] = {
> pbn_pnw},
>
> /*
> + * Intel Tangier
> + */
> + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TNG_UART,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_tng},
> +
> + /*
> * Intel Quark x1000
> */
> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
--
Andy Shevchenko <andriy.shevchenko@xxxxxxxxx>
Intel Finland Oy
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