On Tue, May 27, 2014 at 10:47:05PM -0700, Prasad Koya wrote: > > if char received is garbage then as you hinted it must be that > transmit ready interrupt that is not getting set. This was typo on my part. What I meant to say was that it is the "receive ready interrupt" (not transmit) getting set when it shouldn't be. That is, the fact that DR bit was clear was indeed correct --- the receive FIFO really was empty, but for some reason some other part of the UART was convinced that it should be trying to trigger a receive interrupt, hence the value in IIR. In that case, if you force the DR bit to be set, then you'll be looping forever loading garbage into the tty flip buffer until it overflows. This is why I said you should put in a counter that only does this workaround a limited number of times, and which point you send a printk of the saying "Buggy Intel UART, abandon all hope", and then submit a patch to the kernel cc'ing someone from Intel, in the hopes that they will fix the bug.... Cheers, - Ted -- To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
