Hi,
On Mon, May 26, 2014 at 2:56 AM, Maxime Ripard
<maxime.ripard@xxxxxxxxxxxxxxxxxx> wrote:
> On Fri, May 23, 2014 at 03:51:12PM +0800, Chen-Yu Tsai wrote:
>> Some clock modules on the A31 use PLL6x2 as one of their inputs.
>> This patch changes the PLL6 implementation for A31 to a divs clock,
>> i.e. clock with multiple outputs that have different dividers.
>>
>> This behavior is consistent with previous SoC's by Allwinner.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx>
>> ---
>> drivers/clk/sunxi/clk-sunxi.c | 11 ++++++++++-
>> 1 file changed, 10 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>> index 6857c6e..339cabc 100644
>> --- a/drivers/clk/sunxi/clk-sunxi.c
>> +++ b/drivers/clk/sunxi/clk-sunxi.c
>> @@ -496,6 +496,7 @@ static const struct factors_data sun6i_a31_pll6_data __initconst = {
>> .enable = 31,
>> .table = &sun6i_a31_pll6_config,
>> .getter = sun6i_a31_get_pll6_factors,
>> + .name = "pll6",
>> };
>>
>> static const struct factors_data sun4i_apb1_data __initconst = {
>> @@ -969,6 +970,14 @@ static const struct divs_data pll6_divs_data __initconst = {
>> }
>> };
>>
>> +static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
>> + .factors = &sun6i_a31_pll6_data,
>> + .ndivs = 1,
>> + .div = {
>> + { .fixed = 2 }, /* P, other */
>> + }
>> +};
>> +
>> /**
>> * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
>> *
>> @@ -1108,7 +1117,6 @@ static const struct of_device_id clk_factors_match[] __initconst = {
>> {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
>> {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
>> {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
>> - {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
>> {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
>> {.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,},
>> {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
>> @@ -1128,6 +1136,7 @@ static const struct of_device_id clk_div_match[] __initconst = {
>> static const struct of_device_id clk_divs_match[] __initconst = {
>> {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
>> {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
>> + {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
>
> Can't the PLL6x2 clock just be a fixed-factor-clock? It would make the
> change trivial, and better fit what it actually is.
Sounds good. I was worried there might be an extra output. The A23 manual
lists a SATA PHY output, which I have no idea where it's used.
On the IRC someone (you?) mentioned the A31 doesn't have native SATA.
I'll rework this using a fixed-factor clock.
Thanks
ChenYu
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